搜索资源列表
bin2bcd
- Binary to BCD converter
shift
- Simple shift register with testbench in vhdl
divisor_n_bits_sin_restauracion
- vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
GUI_Matting
- matlab编写的交互式image matting程序，包括：Poisson，Hillman，Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
EDA
- VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda
proc
- vhdl processor,5 commands,memory,testbench
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
VHDL_io
- 基于VHDL的Testbench读取文件的编写的PDF教程文件，很有用-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
fortestbench
- 基于VHDL的Testbench读取文件的编写的PDF教程文件，很有用-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
arm9verilog
- AMBA AHB verilog Source code
elevator_controller
- vhdl elevator controller with testbench
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench